--------------- FIDO MESSAGE AREA==> TOPIC: 145 ASSEMBLY LANG. Ref: E5W00017Date: 05/25/97 From: DAVID SIMAL Time: 10:49pm \/To: PAUL WANKADIA (Read 2 times) Subj: Re: opcodes Bonjour Paul ! Paul Wankadia crivait le Samedi 24 Mai 1997 All : PW> Does anyone know what happens when the CPU comes across an opcode that PW> it doesn't understand? For example, what happens if a 386 tries to PW> run a 486 or a Pentium opcode? The CPU generates an INT 06 : INVALID OPCODE, it is also called the EXTRA CODE interrupt. It should be possible, using this interrupt to "program" 486 and even pentium instructions for a 386... but I don't know how to do... Amitis, David. --- GoldED/386 2.50+ * Origin: OVER-BBS, +32-81-732.763, 21h30-6h00 (2:293/3407) --------------- FIDO MESSAGE AREA==> TOPIC: 145 ASSEMBLY LANG. Ref: E5W00018Date: 05/26/97 From: BRENT FOSTER Time: 12:00am \/To: BARRY BLOCK (Read 2 times) Subj: implode (cls) BB>Hello all, I saw a shareware implode screen (cls) using way to many bytes, BB>so I tried to see what I could do. This is a first, maybe last draft :-) BB>One problem is, a single timer tick is too long. BB>What else can I use as a timer so that the speed is the same on all machines You just a programable timer..... no problem. I just happen to have the right book for you here then. Pc Programmer's Guide to Low-Level Functions and Interrupts, by Marus Johnson... anyways.. int 08H is called 18.2 times a second... that might help, by if you intercept this vector you MUST call the original procedure 18.2 times a second.. It takes care of a few things for you. There is a PIC (programmable Interval Timer) on the PC here's how to program for it. Port 40H Counter 1 41H counter 2 42H counter 3 43H CONTROL WORD PIT CONTROL WORD FIELDS BITS 7-6 00 Select counter 0 01 " " 1 10 " " 2 11 ILLEGAL 5-4 00 Counter latch command 01 Read/write LSB only 10 Read/Write MSB only 11 Read/Write LSB THEN MSB 3-1 Mode 0 to 5 110 Mode 2 but not recommended 111 Mode 3 but not recommended 0 0 Binary count 1 BCD count Modes 0 interrupt on terminal count 1 hardware triggerable one-shot 2 rate generator 3 square wave mode 4 Software triggered strobe 5 Hardware triggered strobe Continuded in next MSG >>>>>>>>>>>>>>> ___ X OLX 2.1 TD X All hope abandon, ye who enter messages here. --- Maximus 2.02 * Origin: Digital Encounters * Kamloops BC Canada 250/374-6168 (1:353/710) --------------- FIDO MESSAGE AREA==> TOPIC: 145 ASSEMBLY LANG. Ref: E5W00019Date: 05/26/97 From: BRENT FOSTER Time: 12:00am \/To: BARRY BLOCK (Read 2 times) Subj: implode (cls) Using the PIC is not easy, but it will give you accurate time on ALL machines. BTW counter 0 is the system timer counter 1 is for the DRAM refresh counter 2 is tied to the PC speaker. if you want to speed up you computer a little you can lower the DRAM refresh rate.. Works for me, I get about 5% increase... just lower it until you computer starts to crash then bring it back up a bit. Anyways Counter 0 calls int 08H which calls int 1CH to adjust the clock just re-program the clock. save the Int vector for 08H, insert your code for a new 08H (like 1 rep per call or something) and then have your code call the old 08H 18.2 times a second (or your clock will mess up) and that is it. The Wolfman ___ X OLX 2.1 TD X --T-A+G-L-I+N-E--+M-E-A+S-U-R+I-N-G+--G-A+U-G-E-- --- Maximus 2.02 * Origin: Digital Encounters * Kamloops BC Canada 250/374-6168 (1:353/710) --------------- FIDO MESSAGE AREA==> TOPIC: 145 ASSEMBLY LANG. Ref: E5W00020Date: 05/26/97 From: JERRY COFFIN Time: 01:03pm \/To: MORTEN PERRIARD (Read 2 times) Subj: Bug in P2 On (25 May 97) Morten Perriard wrote to Eric Tam... ET> Pentium II has the same bug as P5-60. Floating Poing error. MP> Where have you heard/read that? He misread that. The Pentium Pro and Pentium II have a new and different floating point error. However, the error is much less problematic, at least IMO. The problem arises during conversion of a negative floating point number to an integer. If the floating point number is the correct magnitude, the processor produces an exception that it shouldn't. It should be noted that this is a fairly uncommon thing to do to start with, (most programs work either in floating point or integers, but don't convert between them much.) and that it's easily handled in any case. The problem with the early Pentium was that it was relatively difficult to detect when the error occurred, and relatively difficult to fix it if it did. About the only thing you could do to ensure accuracy was to never use any instructions that involved division, doing all division with some sort of emulation. That's not terribly difficult, but causes a terrible speed hit. By contrast, the current problem causes an exception that's easy to trap. This means it's quite easy to detect when a problem has occurred, and just about as easy to fix it. (basically just return from the interrupt, ignoring that the exception occurred.) Except under extremely unusual circumstances, this wouldn't happen often enough to cause any measurable impact on performance. Later, Jerry. ... The Universe is a figment of its own imagination. --- PPoint 1.90 * Origin: Point Pointedly Pointless (1:128/166.5) --------------- FIDO MESSAGE AREA==> TOPIC: 145 ASSEMBLY LANG. Ref: E5X00000Date: 05/27/97 From: TOM ST DENIS Time: 06:27am \/To: JAMES VAHN (Read 2 times) Subj: Re: Just a quick one :) > How do I put the screen in 80x50 text mode with inline ASM on a TP7 > program? I pascal? Isn't there a built in command for that...? --- GEcho 1.00 * Origin: 872's Home Bbs (613)831-3390 (1:163/133) --------------- FIDO MESSAGE AREA==> TOPIC: 145 ASSEMBLY LANG. Ref: E5X00001Date: 05/27/97 From: TOM ST DENIS Time: 06:30am \/To: ALL (Read 2 times) Subj: INT 06 - Invalid Opcode Yes, when the cpu encounters a byte it doesn't reconize, it issues an Invalid Interrupt (If that fails then it is a GPF, then a SF, DF and TF...anyways...) This applies to Real Mode and Protected Mode. The thing is though... Is that the pentium supports different modes of protected mode that the 486 and below don't offer. So you may be able to pull off a couple of the 586 instructions but not all of them, also you can invent your own opcodes.... TTYL --- GEcho 1.00 * Origin: 872's Home Bbs (613)831-3390 (1:163/133) --------------- FIDO MESSAGE AREA==> TOPIC: 145 ASSEMBLY LANG. Ref: E5X00002Date: 05/26/97 From: BARRY BLOCK Time: 02:09pm \/To: JOHN GARDENIERS (Read 2 times) Subj: diffuse.asm Hello John, BB>> Diffuse.com v1 - Barry Block 5-97 - assemble w/A86 JG> Haven't looked at it yet but have a small suggestion. Instead of JG> moving the cursor why not just turn it off and turn it back on again hen JG> required? A flashing cursor can really detract from an otherwise good JG> screen effect. I'll try it, John. Reason was, after clearing, the cursor was at the bottom of the screen. A normal cls puts the cursor at the top. The screen clears fast enough that the cursor is not noticed. But I will try turning it off to see the effect and how much it increases the code size. Because it's slower (more complicated), it will help the spiral routine James V. posted, in responce to my request to see more clearing routines (hint, hint). Kind regards, Barry --- Terminate 4.00/Pro * Origin: EBO-BBS A'dam +31-20-6002828 (2:280/901.42) --------------- FIDO MESSAGE AREA==> TOPIC: 145 ASSEMBLY LANG. Ref: E5X00003Date: 05/25/97 From: MICHAEL MUELLER Time: 12:00am \/To: PAUL WANKADIA (Read 2 times) Subj: Re: opcodes Hallo Paul, du schriebst in /FIDO/80XXX am 24.05.97: PW> Does anyone know what happens when the CPU comes across an opcode that it PW> doesn't understand? For example, what happens if a 386 tries to run a 86 PW> or a Pentium opcode? It will produce an interrupt 6. This is sometimes used to emalute a co- processor on systems that do not have one. Michael --- CrossPoint v3.11 * Origin: (2:2452/249.3) --------------- FIDO MESSAGE AREA==> TOPIC: 145 ASSEMBLY LANG. Ref: E5X00004Date: 05/26/97 From: MICHAEL MUELLER Time: 12:00am \/To: JOE KOSS (Read 2 times) Subj: Re: Bosskey.Asm - sysreq. Hi Joe, you wrote in /FIDO/80XXX at 24 May 97: JK> In a case such as: JK> JK> mov ss, ds:[foo] JK> mov sp, ds:[bar] JK> JK> The "stack" is invalid inbetwen the two instructions. Any attempts to use JK> it will result in bad ju-ju. But there will be all interrupts disabled beetween does commands. It is a feuture of the 80x86-family chips. Michael --- CrossPoint v3.11 * Origin: (2:2452/249.3) --------------- FIDO MESSAGE AREA==> TOPIC: 145 ASSEMBLY LANG. Ref: E5X00005Date: 05/21/97 From: DORAN MOPPERT Time: 05:26pm \/To: MERVYN BALDWIN (Read 2 times) Subj: Bosskey.Asm - sysreq.asm >It's not the same on the return. Which is major crash problem one. SS:SP re >toasted after the INT 2E call. MB> Need advice re INT 2eh. Have always heard it to be a dodgy INT, prone MB> to cause worst sort of crashes. Is this true? Is it safe to use it MB> instead of EXEC? Are there precautions which make it safer? According to Ralf Brown's listing, int 2eh seems okay provided that the program is not invoked from a batch file (clashes with DOS internal variables). On return all registers are trashed, so you'll need something ke pusha push ds push es mov ax,sp mov cs:[save_SP],ax mov ax,ss mov cs:[save_SS],ax int 2eh cli ; don't want interrupts occuring when the stack is in nowhereland mov ax,cs:[save_SS] mov ss,ax mov ax,cs:[save_SP] mov sp,ax sti pop es pop ds popa ... that should be more or less acceptable ... you might want to chuck it into a proc or somesuch. However, I would recommend using 21/4b for most things - int 2e is really only necessary when you want to call an internal dos command (ie SET, DIR, etc) without reloading the shell. ... \ _ | | | _/ \_____|\ \_ | \\_\ _/ --- FMail/386 1.20 * Origin: Comms Barrier BBS +61.3.9585.1112, +61.3.9583.6119 (3:632/533)